The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductive substrate between the source and drain electrodes. Dielectric materials, such as silicon dioxide, are commonly employed to electrically separate the various gate electrodes in the integrated circuit.
A FinFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three-dimensional transistor formed in a thin fin that extends upwardly from the semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET, the transistor channel is formed along the vertical sidewalls of the fin, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
FIG. 1 illustrates, in a cut away perspective view, a portion of a prior art FinFET integrated circuit (IC) 100. The illustrated portion of IC 100 includes two fins 102 and 104 that are formed from and extend upwardly from a bulk semiconductor substrate 106. A gate electrode 108 overlies the two fins and is electrically insulated from the fins by a gate insulator (not illustrated). End 110 of fin 102 is impurity doped to form the source of a field effect transistor 112 and end 114 of that fin is appropriately impurity doped to form the drain of the FET. Similarly, ends 116 and 118 of fin 104 form the source and drain, respectively, of another FET 120. The illustrated portion of IC 100 thus includes two FETs 112 and 120 having a common gate electrode 108. In another configuration, if source 110 and 116 are electrically coupled together and drains 114 and 118 are electrically coupled together the structure would be a two-fin FinFET having twice the gate width of either FET 112 or 120. Oxide layer 122 forms electrical isolation between fins and between adjacent devices as is needed for the circuit being implemented. The channel of FinFET 112 extends along the sidewall 124 of fin 102 beneath gate electrode 108 as well as along the opposite sidewall not visible in this perspective view. The advantage of the FinFET structure is that although the fin has only the narrow width represented by the arrows 126, the channel has a width represented by at least twice the height of the fin above oxide 122. The channel width thus can be much greater than fin width.
In the fabrication of such FinFET integrated circuits, during front end-of-the-line (FEOL) processing, a plurality of semiconductor devices (e.g., transistors, resistors, capacitors, and the like) are formed on the semiconductive substrate. The semiconductor devices are then locally interconnected during middle-of-the-line (MEOL) processing to produce the integrated circuit, such as a logic circuit or a memory cell. To enable the local interconnection of the semiconductor devices during MEOL processing, device-level conductive structures or “plugs” are formed in ohmic contact with the electrically-active areas of the substrate (commonly designated as “RX”) and the gate conductors (commonly designated as “PC”), and local interconnect conducive lines are formed in ohmic contact with the device-level plugs of the semiconductor device.
In many cases, such as in replacement gate-based processes, the local interconnect lines and device-level plugs are divided into three general categories: (i) trench-with-late-silicide contacts (referred to herein as “TS contacts”) in ohmic contact with RX; (ii) local interconnect lines (referred to herein as “CA contacts”) in ohmic contact with the TS contacts; and (iii) plugs in ohmic contact with PC (referred to herein as “CB contacts”). The TS, CA, and CB contacts are collectively referred to herein as the “local contacts.” The local contacts may also include shared TS/CA/CB contacts, which provide an electrically-bridged connection to both RX and PC. The TS contact can also include a direct liner contact to RX, for instance by means of a Ti/TiN liner, without involving a silicidation and etch process. After formation of the local contacts, the fabrication process advances to back end-of-the-line (BEOL) processing during which additional BEOL layers are formed to globally interconnect the integrated circuits, which are subsequently separated into individual die during wafer dicing.
From one circuit generation or “node” to the next, critical dimensions are continually reduced and pattern densities are continually increased. To enable the production of highly-dense circuit layouts, MEOL patterning processes have been developed wherein multiple masks are utilized to pattern the dielectric layers deposited over the semiconductor devices (e.g., the pre-metal dielectric layer and the overlying inter-metal dielectric layer), which are subsequently filled with metal and polished to produce the local contacts. For instance, immersion lithography can be used for advanced technologies at the 20 nm or 14 nm minimum gate-length nodes. The CA contacts may thus be printed with a first mask and a first illumination source, while the CB contacts are printed with a second mask and a second illumination source. For the 14 nm node, or more advanced nodes further, it can happen for instance that the resolution of the immersion lithography is not good enough to print all CA patterns with one mask. This patterning is then handled using two or even three masks (e.g., three-color CA), and introduces new challenges in terms of overlay and cost with so-called triple-patterning. All the same, the patterning of the CB contacts to gate may require more than one mask (e.g., two-color CB). Thus, in any case, the current state of the art is to employ multiple/separate patterning and etching processes for the formation of CA and CB contacts, for example up to five separate processes (three for CA, two for CB). Separate patterning and etching steps increase the required fabrication time and expense. Separate patterning and etching steps also increase the likelihood of fabrication-related errors, which may result in device failure.
Extreme ultraviolet (EUV) lithography has been developed to allow better resolution of patterns, and carries the potential for instance to resolve all CA contact openings at once (thus, reducing three steps to a single step). Yet, the added costs of the EUV technology make it questionable whether it would be viable economically should its capability be restricted to replace only three immersion lithography steps by one EUV lithography step. Prospects for EUV would be substantially increased, from a cost perspective, if all five separate patterning processes (when performed using immersion lithography) for printing the CA and CB contacts could be resolved into a single patterning process.
Accordingly, it is desirable to provide improved methods for fabricating FinFET integrated circuits focusing on reducing MEOL fabrication time and expense. Particularly, it is desirable to provide such methods that reduce the number of patterning and etching steps required to fabricate the CA and CB local contact openings. Still further, it is desirable to reduce the number of such patterning and etching steps such that it is economically viable to employ EUV lithography in place of conventional immersion lithography. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawing figures and the foregoing technical field and background of this disclosure.